Verilog ALU
Overview
This is my implementation of a simple Arithmetic and Logic Unit (ALU). It consists of four different blocks, each performing a specific functionality. A block can be selected with the "select" (S) input. Within each block, a specific operation can be chosen with the "mode" (M) input. The available operations of the ALU can be seen in the function table below.
The design of the ALU is hierarchical, and the most high-level modules are shown in the image below. All of the design levels are explained on this page, as well as how I implemented them with hardware descriptive language.
Gates
The smallest modules in a hirearchical digital design are the gates. They define the most basic logical behaviour and lay the foundation for the rest of the modules. Below are four examples of different gates that were used in this project.
Combinatorial Logic
I used the gates to construct combinatorial logic modules. These modules perform some small, very specific task. It can for instance be binary addition, shift operations or logical comparisons such as AND.
Full Adder
One of the most fundamental logic blocks in an ALU is the adder circuit. The purpose of this circuit is to perform simple binary addition. This design is especially useful since it can be chained together to perform addition on an arbitrary number of bits.
A full adder consists of two half adders. The reason for this is that a half adder does not have a carry input, which means they can't be chained.
It seems counterintuitive that the carry signal is high even though none of the inputs are high, but the reason for that is that the carry signal gets inverted once more when propagating through the NAND-gate in the full adder.
Blocks
With the combinatorial logic modules, I designed the so called blocks which define the higher-level functionality of the ALU. Each of the four blocks are described below.
Arithmetic Block
The arithmetic block has three different operations: addition, subtraction and multiplication. Performing an addition and a subtraction is logically the same, with the difference being that a subtraction takes the two's complement to make the second value negative. This is set by bit 0 in the mode input.
In the schematic below, the two inputs has been set to 5 and 3. The mode input is set to M=10 which according to the function table corresponds to multiplication. The output correctly displays the number 15.
Shift/Rotate Block
There are four possible operations in the shift/rotate block: rotate right, rotate left, shift right and shift left.
The following schematic has the input 10101010 and M=01, which means that the mode is set to rotate left. The output correctly displays 01010101 which is the rotated value of the input (with a zero extension).
Comparator Block
The comparator can perform comparisons of the following type: greater than, less than, equal and not equal.
The example below has input A=5 and B=5. Since M=10 the mode is set to equal, and the output is thus 1 (with zero extension).
Logic Block
The logic block compares the two inputs with the following four logical operations: AND, OR, NOT and XOR.
The mode is set to M=11, which according to the function table is the XOR-operation.
Complete ALU
This module connects all of the four blocks together. A block is chosen with the select signal, and the block function is chosen with the mode signal. The select signal controls a set of multiplexers so that the correct values propagate to the output of the module.
The following schematic shows a high-level view of the entire ALU. In this example, the ALU is performing a subtraction between the numbers 7 and 5.
Lastly, I created a testbench for the ALU. The purpose of the testbench is to test a bunch of different scenarios in order to verify that the module has the intended functionality. The testbench was simulated in the program ModelSim.
