Engineer in Electronics and Computer Engineering

3-input XOR gate​

3-input XOR gate

I designed a 3-input XOR gate as part of the standard cell library for the KTH 1 µm technology. The implementation was done in Cadence, and the custom gate symbol is shown below.

Schematic

A 3-input gate will have 2^3=8 different combinations, which is shown in the following truth table. To build this gate, I cascaded two 2-input XOR gates, which gives the same logical behavior as a single 3-input XOR gate. I created a schematic that matched this implementation.

Before moving on to the layout, I tested the logic using LogiSim. I wanted to make sure that my schematic implemented the correct truth table, so I simulated a 3-input XOR gate, two cascaded 2-input XOR gates and the transistor implementation. By comparing the output of each stage, I made sure that the schematic worked as intended.

Layout

With the schematic ready and verified, I moved on to the layout. I started by sketching out the routing for a single 2-input XOR gate by hand. This helped me get a good sense of the connections before doing the actual layout in Cadence.

I designed the layout to be scalable, so the routing is mirrored between the two 2-input XOR gates. This makes it easy to extend the design later to a 4- or 5-input XOR gate if needed. The final cell width ended up being 96 µm.

Simulation

After doing the layout, I created a testbench for the gate. The test changes inputs A, B, and C according to the truth table shown earlier.

The graph below shows the testbench result, which confirms that the truth table was implemented correctly. It’s worth noting that this transient simulation only includes the internal parasitics of the transistors and doesn’t account for layout-related effects.

Because the gate is combinatorial, there’s a brief period before the output settles to its final value. As shown in the output plot, a small glitch appears at some of the clock edges. This isn’t an issue when the gate is used inside a sequential circuit, but it limits the maximum clock frequency. For this specific glitch, the propagation delay was around 900 ps.

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